Logic blocks such as programmable logic arrays are well known. U.S. Pat. No. 4,124,899, for example, describes both the background and the uses of programmable logic arrays and field programmable logic arrays. A typical programmable logic array comprises a plurality of inputs leading through an AND array to a set of AND gates. The outputs of the AND gates, referred to as "product terms", feed through an OR array to a set of OR gates. The outputs of the OR gates are essentially the outputs of the programmable logic array, although as described herein the product terms may also be used as outputs and the outputs may be sent through an output cell where they are manipulated in various ways.
The typical AND-OR form of a programmable logic array is somewhat limiting. Certain capabilities are not easily available in the AND-OR form, such as cascade exclusive OR ("XOR") functions, asynchronous register control and clocking, and the emulation of T-type and J-K type flip-flop functions. These functions are useful in programming the array to perform as a comparator, counter, parity generator or arithmetic logic unit. With a typical AND-OR array, designing devices such as these is difficult and uses up a considerable amount of valuable logic resources within the array.
As an example, a cascaded XOR arrangement such as shown in FIG. 1 is very useful in designing arithmetic logic units and parity generators. FIG. 1 shows an XOR gate 10, the output of which feeds an input of an XOR gate 11. A typical AND-OR programmable logic array does not contain an XOR gate. Therefore, if an XOR gate is required, it must be simulated using the AND-OR structure shown in FIG. 2, wherein the outputs of two AND gates 20 and 21 feed the inputs of an OR gate 22. This simulates only a single XOR gate. If a pair of cascaded XOR gates is required, two such arrangements are required. Since an ordinary AND-OR programmable logic array includes only a single set of AND gates feeding a single set of OR gates, this requires that the output of the first simulated XOR gate be fed back through the array again, thereby using up a considerable amount of the limited number of AND and OR gates available in the array.